1. Field of the Invention
The present invention relates to a circuit and method for driving a display device, and more particularly to a driving circuit and method for correcting a pixel signal to be finally applied to a display pixel in consideration of distortion thereof.
2. Description of the Prior Art
A flat panel display such as a liquid crystal display (LCD), an organic electroluminescence (EL) display or a plasma display has been extensively developed. In particular, the LCD is excellent because it is thin and consumes less power, and has provided the mainstream monitor displays in the field of AV equipment and OA equipment.
The LCD has a liquid crystal provided between a pair of opposed substrates. A large number of electrodes for applying an electric field to the liquid crystal to be driven are formed on an opposed internal face of each substrate. A display pixel is formed as a capacitor using the liquid crystal for a dielectric layer. The display pixels are arranged in a matrix. In particular, matrix arrangement of display elements to which a thin film electric field effect transistor (TFT) is connected as a switching element is referred to as an active matrix type. With the active matrix type, a display pixel voltage is sequentially applied and is held for a non-selection period so that display can be continued. Consequently, a display screen of high quality can be obtained.
In recent years, a polycrystalline semiconductor, particularly polysilicon (p-Si), has been used in place of an amorphous semiconductor which has been utilized as a TFT for an active layer, particularly amorphous silicon (a-Si), so that a switching operating speed can be increased. Consequently, an aperture can be enlarged with a reduction in size of the TFT, or high resolution and the like can be obtained by a reduction in a size of the display element. Thus, very high quality can be obtained. Furthermore, it is required that a driving circuit for driving the display element should operate at a higher speed than the display element. However, CMOS can be formed using a p-SiTFT so that the driving circuit can be built integrally in the same substrate. The LCD with a built-in driver can be manufactured at a low cost and an frame portion on the periphery of a display screen can be reduced in size. Consequently, mass production has been desired.
FIG. 1 shows a structure of an LCD module. Composite video signals VIDEO for R, G and B are sent from the outside to a video interface circuit [I/F]. The video interface circuit [I/F] generates predetermined original pixel signals VDR, VDG and VDB. The original pixel signals VDR, VDG and VDB and are sent to a drain driver [D/D] of an LCD panel through a buffer circuit [B/F]. A synchronizing signal SYNC is sent from the outside to a timing controller [T/C] so that various timing control signals are generated. In the video interface circuit [I/F], the original pixel signals VDR, G and B are split and expanded into a plurality of phases on the basis of a sample-and-hold signal generated by the timing controller [T/C] as will be described below in more detail. The drain driver [D/D] samples the original pixel signals VDR, G and B on the basis of a horizontal shift clock and a horizontal start pulse generated by the timing controller [T/C] to control a sampling operation as will be described below. Agate driver [G/D] of the LCD panel is mainly formed by a vertical shift register, and receives a vertical shift clock and a vertical start pulse from the timing controller [T/C].
The LCD panel has a large number of gate lines [GL] and drain lines [DL] arranged vertically and horizontally. At an intersection part, the TFT acting as the switching element, a liquid crystal capacitor [LC] acting as the display pixel connected to the TFT, and an auxiliary capacitor [SC] for charge storage are provided to form the display element. The gate driver [G/D] scans rows to sequentially select the gate line [GL]. The drain driver [D/D] samples original pixel signals and sequentially sends pixel signals in order to drive each display element for a row selection period. The TFT formed in a display section is a p-SiTFT. The gate driver [G/D] and the drain driver [D/D] also have a CMOS constructed by a p-SiTFT having the same structure of the display section p-SiTFT. Thus, the LCD panel and the gate driver [G/D] and drain driver [D/D] are integrated on the same substrate.
FIG. 2 shows a structure of the drain driver, In FIG. 2, a horizontal shift registers [S/R] 61 are provided in an upper stage, a video data lines [VDL] 62 are provided in a middle stage, and a sampling switchs [SW] 63 are provided in a lower stage. Horizontal start pulses STH 1 and STH 2 and horizontal shift clocks SCK 1 and SCK 2 are sent from the timing controller [T/C] to the horizontal shift registers 61. Sampling pulses SP 1 and SP 2 are generated from each output stage of the shift register 61 so that a sampling switch 63 acting as an analog switch is sequentially turned on. Original pixel signals VDR, VDG and VDB for R, G and B are sent from the buffer circuit [B/F] to the video data lines 62. The original pixel signals VDR, VDG and VDB are sent to each drain line [DL] through the sampling switch 63 which is on. A voltage applied when the sampling switch 63 is turned off is sampled as a pixel signal PX. The original pixel signals VDR, VDG and VDB are split and expanded into 4-phase signals for R, G and B in the video interface circuit [I/F]. The 4-phase signals are sent to a video data line 62.
FIG. 3 is a timing chart showing the relationship between 4-phase original pixel data VDL 1, 2, 3 and 4 for R, G and B which are obtained by dividing and expanding an original pixel signal respectively and a shift clocks SCK1, SCK2 of the shift registers.
In this example, a 4-way split is performed. Each video data line 62 serially receives pixel data signal (Dn, Dn+1 . . . ) every four pixels as analog signals having a 1/4 frequency on a time basis. In other words, the same pixel data for 4 dot periods are transmitted to each video data line. A sampling period, is a period for which a video data signal is sent to each four corresponding drain lines for R. G. B. through a transfer gate [SW] 63 is the last of the four dot periods and sampling is carried out at the end of the sampling period. Therefore, a delay of an original pixel signal is recovered during sampling so that an accurate pixel signal voltage is sampled.
A waveform of the original pixel signal is distorted by an integrating circuit having a parasitic resistance and a parasitic capacitance in the drain driver [D/D]. Such a distortion decreases an amplitude of a pixel signal voltage. Consequently, brightness or contrast ratio is reduced. In particular, a significant uneveness in quality of display is caused by the distortion of the waveform on an end distant from an end where the original pixel signal is sent out or a central portion of a screen in a display section in which pixels are arranged in a matrix. Furthermore, this problem has become remarkable with an increase in size of the substrate.
Referring to the same video data line 62, a pixel signal sent in a previous column affects a pixel signal voltage to be sent to a next column. As a result, the contents of display in some columns affect display in a column provided several columns apart corresponding to the split number. In case of 4-way split, for example, display in some columns affects a column provided four columns apart. In the dot sequential driving operation, furthermore, a signal is also distorted after sampling, that is, by an integrating circuit having a parasitic resistance and a parasitic capacitance of the drain line [DL], a TFT, a liquid crystal capacitor [LC] and an storage capacitor [SC]. Therefore, distortion of data to be finally written to a pixel cannot be ignored. Thus, if display information in a certain position affects a distant display position, a whole display screen is visually recognized as a ghost. Consequently, the quality of the display is deteriorated.
Furthermore, if a difference between a previous pixel signal voltage and a subsequent pixel signal voltage is great, the previous pixel signal voltage affects the next pixel signal voltage more greatly than in the case where the same difference is small. More specifically, if the difference between the previous pixel signal voltage and the subsequent pixel signal voltage is great, it takes a long time to change an original pixel signal voltage. For this reason, the subsequent pixel signal voltage is shifted by a level of the previous pixel signal voltage.
Such a problem can be solved to some extent by splitting the original pixel signal into a plurality of phases and reducing a frequency. However, less effects are obtained by a further reduction in a sampling period which is caused by high resolution of a display, and an increase in a parasitic capacitance and a parasitic resistance of a signal path which is generated by an increase in a screen size of the display.
In order to solve such a problem, it can be proposed that the split number should be further increased. However, this proposal is not preferable because structures of the signal processing circuit and the drain driver [D/D] become complicated and a cost of the circuit is increased.